Technical Field
The present disclosure relates to semiconductor technology and more particularly, to a tunneling nanotube field effect transistor and manufacturing method thereof.
Description of the Related Art
According to Moore's Law, VLSI (Very Large Scale Integration) circuit performance is improved and device cost is reduced as feature sizes in traditional MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) continue to decrease. However, when device dimensions are reduced to sub-micron or nanometer scale (for example, below the 22 nm node), challenges in semiconductor device fabrication and performance arise. According to the 2009 International Technology Roadmap for Semiconductors (ITRS), these challenges include electron tunneling through the short channel and thin insulating film, which may cause current leakage, short channel effects, passive power consumption, as well as changes in the device structure and doping profile.
Some of the above challenges may be overcome by replacing the conventional MOSFET with carbon nanotube field effect transistors (CNTFETs). The use of CNTFETs can also help to further reduce device dimensions.
The prior art discloses a carbon nanotube field effect transistor having a planar structure. In the planar-type CNTFET, a gate is formed on a substrate and a carbon nanotube is formed above the gate. A source region and a drain region are formed on the substrate on the respective ends of the carbon nanotube.
The prior art also discloses a carbon nanotube field effect transistor having a wrap-around structure. In the wrap-around type CNTFET, a trench is formed on the substrate and a carbon nanotube is formed on the trench. A gate is formed surrounding the carbon nanotube in the trench. A source region and a drain region are formed on the substrate on the respective ends of the carbon nanotube.
However, both of the above prior art CNTFETs have high operating voltages which lead to high energy consumption, and are therefore not well-suited for CMOS technology and VLSI. For VLSI compatibility, a tunneling nanotube field effect transistor having an operating voltage of 0.1 V and a subthreshold oscillation characteristic of less than 60 mV/decade is preferred.